Modern communication systems often seek to transmit a large amount of information in a short period of time. Early solutions sought to increase the clock speed of communications systems, thereby increasing the rate such systems could process serial input. While clock speeds have increased, such increases are sometimes insufficient or inappropriate for a particular application. As such, industry has developed alternative approaches to high-speed data transmission.
One such approach to provide high-speed bandwidth is a high speed serial (HSS) implementation referred to as “serialization/deserialization” (SERDES). Generally, a SERDES transmitter divides a serial signal into a number of parallel signals for parallel transmission to a SERDES receiver. Generally, a SERDES receiver recombines the parallel signals into the original serial signal.
Typical SERDES receivers include a variable gain amplifier (VGA). Common SERDES VGA applications use differential signals. As such, VGAs are frequently subject to common mode voltage mismatches caused by the ordinary operation of field effect transistors (FETs), current mirrors, and various passive elements of the VGA.
Typical systems use Inter-Digital Analog Converters (IDACs) to offset common mode voltage mismatches. Typical IDAC-based approaches modulate a current flowing through a specified termination resistor, calibrated to the common mode offset. However, this approach frequently expends significant power, which contributes to the overhead for the VGA itself and the SERDES receiver as a whole.